Sitao Huang
Biography
Sitao Huang, Ph.D., is Assistant Professor in the Department of Electrical Engineering and Computer Science at the University of California, Irvine. A scholar in the field of computer architecture and hardware acceleration, Huang focuses on hardware architecture and system optimization for high-efficiency computing, programming languages and compilers for hardware accelerators, and design automation for heterogeneous systems. Huang received a Ph.D. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign in 2021.
Huang is a recipient of the NSF CAREER Award (2025) and was named a DARPA Riser in the Class of 2022. Huang's research has been recognized with multiple best paper awards, including at the ACM/SPEC International Conference on Performance Engineering (2025) and the Conference on Intelligent Data Engineering and Automated Learning (2021). Huang's work on sparse deep neural network acceleration received an Honorable Mention at the IEEE HPEC Graph Challenge (2019), and Huang's team won first place in the Design Automation Conference System Design Contest (2019).
Huang has held research internships at Xilinx Research Labs, Microsoft Research, Synopsys, Microsoft Research Asia, and the VAST Lab at UCLA. Huang has published extensively in computer architecture and design automation venues, with work appearing in conferences such as ASPLOS, DAC, ICCAD, and FPGA, and journals including IEEE Transactions on Computers and ACM Transactions on Architecture and Code Optimization. Huang serves as Associate Editor for ACM Transactions on Reconfigurable Technology and Systems and as Artifact Evaluation Co-chair for the ISFPGA conference.
Return to topEducation
- Ph.D. in Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 2021
- M.S. in Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 2017
- B.Eng. in Electronic Engineering, Tsinghua University, 2014
Distinctions
- DARPA Riser, Class of 2022, 2022
- NSF CAREER Award, 2025
- ACM/SPEC International Conference on Performance Engineering (ICPE 2025) Best Paper Award (Artifact Track), 2025
- Conference on Intelligent Data Engineering and Automated Learning (IDEAL 2021) Best Paper Award, 2021
- IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2021) Best Paper Candidate, 2021
- IEEE HPEC Graph Challenge 2019 Honorable Mention, 2019
- IEEE/ACM Design Automation Conference 2019 (DAC 2019) System Design Contest First Place, 2019
- IEEE HPEC Graph Challenge 2018 Student Innovation Award, 2018
- Design Automation Conference 2018 (DAC 2018) System Design Contest Third Place, 2018
- UIUC ECE Sundaram Seshu International Student Fellowship, 2019
Areas of Expertise
- Hardware Accelerator Design
- High-Level Synthesis Compilation
- FPGA Programming Frameworks
- Heterogeneous System Optimization
- Sparse Neural Network Acceleration
- Hyperdimensional Computing Methods
- Binary Transformer Architectures
Recent Publications
- Yifan Zhang, Xiaoyu Niu, Hongzheng Tian, Yanjun Zhang, Bo Yu, Shaoshan Liu, Sitao Huang, “A Sparsity-Aware Autonomous Path Planning Accelerator with HW/SW Co-Design and Multi-Level Dataflow Optimization”, ACM Transactions on Architecture and Code Optimization, vol. 22, no. 3, pp. 1-25, 2025.
- Ye Qiao, Zhiheng Chen, Yian Wang, Yifan Zhang, Yunzhe Deng, Sitao Huang, “COBRA: Algorithm-Architecture Co-optimized Binary Transformer Accelerator for Edge Inference”, 2025. Presented at IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
- Ye Qiao, Haocheng Xu, Yifan Zhang, Sitao Huang, “MONAS: Efficient Zero-Shot Neural Architecture Search for MCUs”, 2025. Presented at IEEE International Joint Conference on Neural Networks (IJCNN).
- Jingcheng Li, Ye Qiao, Haocheng Xu, Sitao Huang, “RSEND: Retinex-based Squeeze and Excitation Network with Dark Region Detection for Efficient Low Light Image Enhancement”, 2025. Presented at IEEE International Joint Conference on Neural Networks (IJCNN).
- Kun Wu, Jeongmin Brian Park, Xiaofan Zhang, Mert Hidayetoğlu, Vikram Sharma Mailthody, Sitao Huang, Steve Lumetta, Wen-mei Hwu, “SSDTrain: An Activation Offloading Framework to SSDs for Faster Large Language Model Training”, 2025. Presented at ACM/IEEE Design Automation Conference (DAC).
- Hongzheng Tian, Alok Mishra, Zhiheng Chen, Rolando Pablo Hong Enriquez, Dejan Milojicic, Eitan Frachtenberg, Sitao Huang, “HeteroBench: Multi-kernel Benchmarks for Heterogeneous Systems”, 2025. Presented at ACM/SPEC International Conference on Performance Engineering (ICPE).
- Junyao Wang, Haocheng Xu, Yonatan G. Achamyeleh, Sitao Huang, Mohammad Al Faruque, “HyperDetect: A Real-Time Hyperdimensional Solution for Intrusion Detection in IoT Networks”, IEEE Internet of Things Journal, vol. 11, no. 8, pp. 14844-14856, 2024.
- Yanjun Zhang, Xiaoyu Niu, Yifan Zhang, Hongzheng Tian, Bo Yu, Shaoshan Liu, Sitao Huang, “A Sparsity-Aware Autonomous Path Planning Accelerator with Algorithm-Architecture Co-Design”, 2024. Presented at 2024 International Conference on Computer-Aided Design (ICCAD).
- Kun Wu, Mert Hidayetoğlu, Xiang Song, Sitao Huang, Da Zheng, Israt Nisa, Wen-mei Hwu, “Hector: An Efficient Programming and Compilation Framework for Implementing Relational Graph Neural Networks in GPU Architectures”, 2024. Presented at ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).
- Haocheng Xu, Haotian Hu, Sitao Huang, “Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models”, 2024. Presented at 2024 IEEE LLM Aided Design Workshop (LAD).
- Xiaofan Zhang, Yao Chen, Cong Hao, Sitao Huang, Yuhong Li, Deming Chen, “Compilation and Optimizations for Efficient Machine Learning on Embedded Systems”, Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer Nature, 2023.
- Genghan Zhang, Yuetong Zhao, Yanting Tao, Zhongming Yu, Guohao Dai, Sitao Huang, Yuan Wen, Pavlos Petoumenos, Yu Wang, “Sgap: Towards Efficient Sparse Tensor Algebra Compilation for GPU”, CCF Transactions on High Performance Computing, vol. 5, pp. 210–227, 2023.
- Yifan Zhang, Arnav Vaibhav Malawade, Xiaofang Zhang, Yuhui Li, DongHwan Seong, Mohammad Abdullah Al Faruque, Sitao Huang, “CARMA: Context-Aware Runtime Reconfiguration for Energy-Efficient Sensor Fusion”, 2023. Presented at ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED).
- Junyao Wang, Sitao Huang, Mohsen Imani, “DistHD: A Learner-Aware Dynamic Encoding Method for Hyperdimensional Classification”, 2023. Presented at IEEE/ACM Design Automation Conference (DAC).
- Hongzheng Tian, Shining Yang, Yoonha Cha, Jinwen Wu, Yuqi He, Sitao Huang, “PyAIE: A Python-based Programming Framework for Versal ACAP Platforms”, 2023. Presented at IEEE/ACM Design Automation Conference (DAC) Late Breaking Results.
- Junyao Wang, Hanning Chen, Mariam Issa, Sitao Huang, Mohsen Imani, “Scalable and Efficient Hyperdimensional Computing for Network Intrusion Detection”, 2023. Presented at IEEE/ACM Design Automation Conference (DAC) Late Breaking Results.
- Sitao Huang, Kun Wu, Hyunmin Jeong, Chengyue Wang, Deming Chen, Wen-mei Hwu, “PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow”, IEEE Transactions on Computers (TC), vol. 70, no. 12, pp. 2015–2028, 2021.
- Seung Won Min, Kun Wu, Sitao Huang, Mert Hidayetoglu, Jinjun Xiong, Eiman Ebrahimi, Deming Chen, Wen-mei Hwu, “Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture”, Proceedings of the VLDB Endowment, vol. 14, no. 11, pp. 2087–2100, 2021.
- Mang Yu, Sitao Huang, Deming Chen, “Chimera: A Hybrid Machine Learning-Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis”, pp. 524–536, 2021. Presented at International Conference on Intelligent Data Engineering and Automated Learning (IDEAL).
Contact Information
Website: https://sitaohuang.com
Email: sitaoh@uci.edu
Address: 3215 Engineering Hall
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Last updated on 5/14/2026.