Priya Sundararajan
Biography
Priya Sundararajan is a Specialist in the Department of Physics and Astronomy at the University of California, Irvine, where she contributes to high-energy physics experiments including ATLAS at CERN and DUNE at Fermilab. She holds an M.S. in Computer Science and Engineering from Pennsylvania State University. With over 20 years of experience in FPGA firmware design and embedded systems, Sundararajan has worked across academic research and commercial applications, including positions at Xerox Corporation, HCL America, Availink Inc, and Xilinx Inc.
At UC Irvine, Sundararajan serves as System Engineer and Level 4 Manager for the CERN ATLAS Event Filter Tracking project, leading the system design and FPGA implementation of track reconstruction on a heterogeneous CPU-FPGA-GPU platform using the AMD U250. She proposed and oversaw deployment of a heterogeneous testbed at CERN for validating tracking algorithms and has standardized data formats and automated build workflows across the collaboration. She has also contributed to the ATLAS Muon Trigger and Readout Subsystem, developing firmware for the Monitored Drift Tube Trigger Processor on the Xilinx VU13P platform and representing the ATLAS Muon community at the Full Design Review. For the DUNE Near Detector, she develops and maintains FPGA SoC firmware for the AMD Zynq-7000-based PACMAN pixel readout board.
Prior to joining UC Irvine, Sundararajan led FPGA accelerator platform development at HCL America, including architecture and delivery of Xilinx Zynq UltraScale+ MPSoC and Altera Arria V-based systems with OpenCL support for heterogeneous computing. At Xerox Corporation, she independently led firmware design for Image Output Terminal solutions and contributed to image processing algorithms for production printers. She has published technical papers on FPGA performance optimization and thermal characterization, and has presented tutorials and technical reviews at CERN workshops and international conferences.
Return to topEducation
- MS in Computer Science and Engineering, Pennsylvania State University, 2006
- Bachelor's degree, National Institute of Technology, Trichy, India, 1999
Areas of Expertise
- FPGA Firmware Design
- High Energy Physics Instrumentation
- Heterogeneous Computing Architectures
- Real-Time Track Reconstruction
- Hardware Trigger Systems
- Pixel Detector Readout
- OpenCL Kernel Development
Recent Publications
- Longarini Iacopo, Sundararajan Priya, Benjamin J. Rosser, “Monitoring of FPGA algorithms using SpyBuffers”, 2024. Presented at FPGA Developers Forum(FDF) 2023.
- Rimsky Rojas on behalf of the ATLAS TDAQ collaboration, “Status of the MDT Trigger Processor for the ATLAS Level-0 Muon trigger at the HL-LHC” (opens in new tab), JINST, 2024.
- Haider Abidi On behalf of the ATLAS TDAQ collaboration, “Development of an FPGA based track reconstruction pipeline for the ATLAS Event Filter” (opens in new tab), 2024. Presented at Conference on Computing in High Energy Physics(CHEP) 2024.
- Oliver, Jason, Camplani, Alessandra, Dittmeier, Sebastian, Abidi, Haider, Sundararajan, Priya, “Event Filter Tracking (EF Tracking) Internal data formats.”, ATL-COM-DAQ-2024-019, 2024.
- Sundararajan Priya, Ntekas Kostas for the ATLAS Collaboration, “New developments in the MDT Trigger Processor for the ATLAS Level-0 Muon Trigger at the High Luminosity LHC” (opens in new tab), Journal of Instrumentation, vol. 18, 2023.
- Sundararajan Priya for the ATLAS Collaboration, “The hardware prototype and firmware integration of the MDT Trigger Processor for the ATLAS Level-0 Muon Trigger at the HL-LHC”, 2023. Presented at IEEE (NSS/MIC 2023).
- P.Sundararajan, A.Camplani, S.Dittmeier, P.Mastrandrea, A.Taffard, M. Wynne, Z.Cui, V.Boisvert, S.Majewski, “Event Filter Tracking Report on Interface between CPU and FPGA, GPU compute cores in a heterogeneous system”, ATLAS-TDR-029-ADD-1, 2023.
- Ntekas Kostas for the ATLAS Collaboration, “Recent Developments in the MDT Trigger Processor for the ATLAS Level-0 Muon Trigger at the HL-LHC” (opens in new tab), 2022.
- ATLAS TDAQ Collaboration, “Technical Design Report for the Phase-II Upgrade of the ATLAS Trigger and Data Acquisition System - EF Tracking Amendment”, ATLAS-TDR-029-ADD-1, 2022.
- Loustau De Linares Guillermo for the ATLAS Collaboration, “The MDT Trigger Processor development for the ATLAS Level-0 Muon Trigger at HL-LHC”, 2021. Presented at Topical Workshop on Electronics for Particle Physics(TWEPP) 2021.
- Cieri Davide for the ATLAS Collaboration, “Hardware demonstrator of the Phase II ATLAS Level-0 MDT Trigger processor” (opens in new tab), 2019.
- Priya Sundararajan, Krishnamurthy S., Narayanan, V., Chaudhary, K., Jayaraman, R., “Performance Improvement through Timing Driven Reconfiguration of Black Boxes in FPGAs” (opens in new tab), pp. 105-106, 2006. Presented at 2006 IEEE International SOC Conference, Austin, TX, USA.
- Priya Sundararajan, Aman Gayasen, Narayanan, V., Tuan, T., “Thermal Characterization and Optimization in Platform FPGAs” (opens in new tab), 2006. Presented at 2006 International Conference on Computer-Aided Design, ICCAD, San Jose, CA, USA.
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Last updated on 6/18/2026.